1. Field of the Invention
The present invention relates to error correction of a Flash memory control chip, and more particularly, to a method for enhancing error correction capability of a controller of a memory device without need to increase a basic error correction bit count of an Error Correction Code (ECC) engine, and to an associated memory device and a controller thereof.
2. Description of the Prior Art
As technologies of Flash memories progress in recent years, many kinds of portable memory devices (e.g. memory cards respectively complying with SD/MMC, CF, MS, and XD standards) or solid state drives (SSDs) equipped with Flash memories are widely implemented in various applications. Therefore, the control of access to Flash memories in these memory devices has become an important issue.
Taking NAND Flash memories as an example, they can mainly be divided into two types, i.e. Single Level Cell (SLC) Flash memories and Multiple Level Cell (MLC) Flash memories. Each transistor that is considered a memory cell in SLC Flash memories only has two charge levels that respectively represent a logical value 0 and a logical value 1. In addition, the storage capability of each transistor that is considered a memory cell in MLC Flash memories can be fully utilized. More specifically, the voltage for driving memory cells in the MLC Flash memories is typically higher than that in the SLC Flash memories, and different voltage levels can be applied to the memory cells in the MLC Flash memories in order to record information of at least two bits (e.g. binary values 00, 01, 11, or 10) in a transistor that is considered a memory cell. Theoretically, the storage density of the MLC Flash memories may reach twice the storage density of the SLC Flash memories, which is considered good news for NAND Flash memory manufacturers who encountered a bottleneck of NAND Flash technologies.
As MLC Flash memories are cheaper than SLC Flash memories, and are capable of providing higher capacity than SLC Flash memories while the space is limited, MLC Flash memories have been a main stream for implementation of most portable memory devices on the market. However, various problems of the MLC Flash memories have arisen due to their unstable characteristics. Although there are some solutions proposed by the related art in response to these problems, it seems unlikely that the related art gives consideration to both operation performance and system resource management. As a result, no matter which solution is chosen, a corresponding side effect typically exists.
More particularly, the error correction implemented according to the related art typically does not use up all the storage space of a Flash memory, where the remaining storage space of the Flash memory cannot be utilized for storing data, which is really wasteful. Please note that a typical reason why the related art does not use up all the storage space of the Flash memory is typically that, once the basic error correction bit count (which typically represents the error correction capability measured in bits with respect to a specific amount of data) of an Error Correction Code (ECC) engine is increased, the associated costs of the ECC engine are greatly increased. For example, with respect to 1K bytes (i.e. 1024 bytes) of data, increasing the ECC engine encoding/decoding bit count from 24 bits to 36 bits will cause the chip area of the ECC engine to greatly increase, where the new value of chip area may reach approximately 1.5 times the original value of the chip area. Therefore, a novel method is required for enhancing the control of data access of a Flash memory in a memory device, in order to give consideration to both operation performance and system resource management.